The present invention relates to a voltage regulator. More specifically, the present invention relates to a high efficiency switching voltage regulator capable of operating in either one of two modes.
Typically, voltage regulator circuits provide a constant output voltage of a predetermined value by monitoring the output and using feedback to keep the output constant. In a typical pulse width modulation (PWM) regulator circuit, a square wave is provided to the control terminal of the switching device to control its on and off states. Since increasing the on time of the switching device increases the output voltage, and vice versa, the output voltage may be controlled by manipulating the duty cycle of the square wave. This manipulation is accomplished by a control circuit which continually compares the output voltage to a reference voltage and adjusts the duty cycle of the square wave to maintain a constant output voltage.
When the switching device is an MOS transistor, a significant amount of power is used to periodically charge the gates of the switching transistors. As the switching frequency increases, more power is lost. If the switching frequency is too low and the output current of the regulator is high, the output voltage of the regulator will be difficult to filter and convert to a DC voltage. Hence, the switching frequency must be kept relatively high. When the output current is low, the relatively high power loss due to controlling the switching transistors results in a low efficiency (output power/total power consumed) regulator.
A continuing challenge in the design of voltage regulators is to reduce the power loss in the regulator circuit and thereby increase its efficiency. As such, the power dissipate  dissipated in the control circuitry and switching circuitry of the PWM regulator is of great concern.
A switching voltage regulator is disclosed which is capable of operating in either a pulse frequency modulation (PFM) or pulse-width modulation (PWM) mode. The voltage regulator achieves high efficiency by automatically choosing the more efficient mode of regulation based on a continuous monitoring of the output current and the output voltage. The regulator operates in PFM mode when the regulator generates a small output current and switches to PWM operation when the regulator generates a moderate to large output current.
A PFM mode of voltage regulation provides better efficiency at small output current levels than does a PWM mode. First, a PFM mode requires a  fewer turn-on transitions to maintain a constant output voltage than does a PWM mode of voltage regulation, thus resulting in a lower gate-drive power dissipation for PFM mode. Second, since a PFM mode can be achieved with a much simpler control circuit having fewer components, the power dissipation in the control loop of a PFM mode is less than that of the control loop of a PWM mode.
However, when the output current reaches a moderate level, a PFM mode of voltage regulation becomes impractical, since the maximum output current available from a PFM mode is generally much less than that available from a PWM mode. Thus, the present invention switches from a PFM mode of operation to a PWM mode of operation when the output current exceeds a predetermined level.
A novel technique to determine when to operate in PWM or PFM mode is also described along with a novel PFM type voltage regulator.